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CY7C68000A
MoBL-USBTM TX2 USB 2.0 UTMI Transceiver
MoBL-USBTM TX2 Features

Supports transmission of Resume Signaling 3.3V Operation Two package options: 56-pin QFN and 56-pin VFBGA All required terminations, including 1.5 Kohm pull up on DPLUS, are internal to chip Supports USB 2.0 Test Modes
UTMI-compliant and USB 2.0 certified for device operation Operates in both USB 2.0 High Speed (HS), 480 Mbits/second, and Full Speed (FS), 12 Mbits/second Optimized for Seamless Interface with Intel Monahans Applications Processors Tri-state Mode enables sharing of UTMI Bus with other devices Serial-to-Parallel and Parallel-to-Serial Conversions 8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional External Data Interface Synchronous Field and EOP Detection on Receive Packets Synchronous Field and EOP Generation on Transmit Packets Data and Clock Recovery from the USB Serial Stream Bit stuffing and unstuffing; Bit Stuff Error Detection Staging Register to manage Data Rate variation due to Bit stuffing and unstuffing 16-bit 30 MHz and 8-bit 60 MHz Parallel Interface Ability to switch between FS and HS terminations and signaling Supports detection of USB Reset, Suspend, and Resume Supports HS identification and detection as defined by the USB 2.0 Specification
(R)
The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial and deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The MoBL-USB TX2 provides a high speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth. This enables the system designer to keep the complex high speed analog USB components external to the digital ASIC. This decreases development time and associated risk. A standard USB 2.0-certified interface is provided and is compliant with Transceiver Macrocell Interface (UTMI) specification version 1.05 dated 3/29/2001. This product is also optimized to seamlessly interface with Monahans -P & -L applications processors. It has been characterized by Intel and is recommended as the USB 2.0 UTMI transceiver of choice for its Monahans processors. It is also capable of tri-stating the UTMI bus, while suspended, to enable the bus to be shared with other devices. Two packages are defined for the family: 56-pin QFN and 56-pin VFBGA. The functional block diagram follows.
Logic Block Diagram
Tri_state
Cypress Semiconductor Corporation Document #: 38-08052 Rev. *G
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 5, 2008
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CY7C68000A
Applications
Mobile Applications

Smart Phones PDA Phones Gaming Phones MP3 players Portable Media Players (PMP) GPS Tracking Devices Cameras Scanners DSL Modems Memory Card Readers
An on-chip phase-locked loop (PLL) multiplies the 24 MHz oscillator up to 30 or 60 MHz, as required by the transceiver parallel data bus. The default UTMI interface clock (CLK) frequency is determined by the DataBus16_8 pin.
Buses
The two packages enable a 8- or 16-bit bidirectional data bus for data transfers to a controlling unit.
Suspend and Tri-state Modes
When the MoBL-USB TX2 is not in use, the processor reduces power consumption by putting it into Suspend mode using the Suspend pin. While in Suspend mode, Tri-state mode may be enabled, which tri-states all outputs and IOs, enabling the UTMI interface pins to be shared with other devices. This is valuable in mobile handset applications, where GPIOs are at a premium. The outputs and IOs are tri-stated ~50ns when Tri-state mode is enabled, and are driven ~50ns when Tri-state mode is disabled. All inputs must not be left floating while in Tri-state mode. When resuming after a suspend, the PLL stabilizes approximately 200 s after the suspend pin goes high.
Consumer Applications

Non-Consumer Applications

Networking Wireless LAN Home PNA
Reset Pin
An input pin (Reset) resets the chip. This pin has hysteresis and is active HIGH according to the UTMI specification. The internal PLL stabilizes approximately 200 s after VCC has reached 3.3V.
Functional Overview
The functionality of this chip is described in the following sections:
Line State
The Line State output pins LineState[1:0] are driven by combinational logic and may be toggling between the `J' and the `K' states. They are synchronized to the CLK signal for a valid signal. On the CLK edge, the state of these lines reflect the state of the USB data lines. Upon the clock edge the `0' bit of the LineState pins is the state of the DPLUS line and the `1' bit of LineState is the DMINUS line. When synchronized, the setup and hold timing of the LineState is identical to the parallel data bus.
USB Signaling Speed
The MoBL-USB TX2 operates at two of the rates defined in the USB Specification 2.0, dated 4/27/2000.

Full speed, with a signaling bit rate of 12 Mbps High speed, with a signaling bit rate of 480 Mbps
The MoBL-USB TX2 does not support the LS signaling rate of 1.5 Mbps.
Transceiver Clock Frequency
The MoBL-USB TX2 has an on-chip oscillator circuit that uses an external 24 MHz (100 ppm) crystal with the following characteristics:

Full-speed versus High-speed Select
The FS versus HS is done through the use of both XcvrSelect and the TermSelect input signals. The TermSelect signal enables the 1.5 Kohm pull up on to the DPLUS pin. When TermSelect is driven LOW, a SE0 is asserted on the USB providing the HS termination and generating the HS Idle state on the bus. The XcvrSelect signal is the control that selects either the FS transceivers or the HS transceivers. By setting this pin to a `0' the HS transceivers are selected and by setting this bit to a'1' the FS transceivers are selected.
Parallel resonant Fundamental mode 500 W drive level 27 to 33 pF (5% tolerance) load capacitors
Document #: 38-08052 Rev. *G
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CY7C68000A
Operational Modes
The operational modes are controlled by the OpMode signals. The OpMode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. These modes take effect immediately and take precedence over any pending data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input. OpMode[1:0] 00 01 10 11 Mode 0 1 2 3 Description Normal operation Non-driving Disable Bit Stuffing and NRZI encoding Reserved
Mode 0 enables the transceiver to operate with normal USB data decoding and encoding. Mode 1 enables the transceiver logic to support a soft disconnect feature that tri-states both the HS and FS transmitters, and removes any termination from the USB, making it appear to an upstream port that the device is disconnected from the bus. Mode 2 disables Bit Stuff and NRZI encoding logic so `1's loaded from the data bus becomes `J's on the DPLUS/DMINUS lines and `0's become `K's.
DPLUS/DMINUS Impedance Termination
The CY7C68000A does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0. Incorporating these resistors also reduces the pin count on the part.
Document #: 38-08052 Rev. *G
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CY7C68000A
Pin Configurations
The following pages illustrate the individual pin diagrams that are available in the 56-pin QFN and 56-pin VFBGA packages. The packages offered use either an 8-bit (60 MHz) or 16-bit (30 MHz) bus interface. Figure 1. CY7C68000A 56-pin QFN Pin Assignment
DataBus16_8
Reserved
Uni_bidi
TXValid
ValidH
56
GND
CLK
VCC
55
VCC
D0
D1
D2
D3
D4
54
53
52
51
50
49
48
47
46
45
44
43
TXReady Suspend Reset AVCC XTALOUT XTALIN AGND AVCC DPLUS DMINUS AGND XcvrSelect TermSelect OpMode0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
42 41 40 39 38 37
GND D5 Reserved D6 D7 D8 D9 Reserved D10 D11 VCC D12 GND D13
CY7C68000A
56-pin QFN
36 35 34 33 32 31 30 29
Document #: 38-08052 Rev. *G
OpMode1
GND
VCC
LineState0
LineState1
GND
RXValid
RXActive
RXError
Tri_state
Reserved
D15
D14
VCC
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CY7C68000A
Figure 2. CY7C68000A 56-pin VFBGA Pin Assignment
1 2 3 4 5 6 7 8
A
1A
2A
3A
4A
5A
6A
7A
8A
B
1B
2B
3B
4B
5B
6B
7B
8B
C
1C
2C
3C
4C
5C
6C
7C
8C
D
1D
2D
7D
8D
E
1E
2E
7E
8E
F
1F
2F
3F
4F
5F
6F
7F
8F
G
1G
2G
3G
4G
5G
6G
7G
8G
H
1H
2H
3H
4H
5H
6H
7H
8H
Document #: 38-08052 Rev. *G
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CY7C68000A
Pin Descriptions
Table 1. Pin Descriptions QFN VFBGA 4 8 7 11 9 10 49 48 46 44 43 41 39 38 37 36 34 33 31 29 27 26 50 3 H1 H5 H4 H8 H6 H7 G8 G7 G5 G3 G2 F8 F6 F5 F4 F3 F1 G4 E1 D8 G1 E2 A1 B2 Name AVCC AVCC AGND AGND DPLUS DMINUS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLK Reset Type Power Power Power Power I/O/Z I/O/Z I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Input N/A Clock This output is used for clocking the receive and transmit parallel data on the D[15:0] bus. Active HIGH Reset Resets the entire chip. This pin can be tied to VCC through a 0.1-F capacitor and to GND through a 100 K resistor for a 10-ms RC time constant. Transceiver Select This signal selects between the Full Speed (FS) and the High Speed (HS) transceivers: 0: HS transceiver enabled 1: FS transceiver enabled Termination Select This signal selects between the Full Speed (FS) and the High Speed (HS) terminations: 0: HS termination 1: FS termination Suspend Places the CY7C68000A in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operations. While suspended, TermSelect must always be in FS mode to ensure that the 1.5 Kohm pull up on DPLUS remains powered. 0: CY7C68000A circuitry drawing suspend current 1: CY7C68000A circuitry drawing normal current Bidirectional Data Bus This bidirectional bus is used as the upper eight bits of the data bus when in the 16-bit mode, and not used when in the 8-bit bidirectional mode. Under the 8-bit unidirectional mode these bits are used as outputs for data, selected by the TxValid signal. Default N/A N/A N/A N/A Z Z Description[1] Analog VCC This signal provides power to the analog section of the chip. Analog VCC This signal provides power to the analog section of the chip. Analog Ground Connect to ground with as short a path as possible. Analog Ground Connect to ground with as short a path as possible. USB DPLUS Signal Connect to the USB DPLUS signal. USB DMINUS Signal Connect to the USB DMINUS signal. Bidirectional Data Bus This bidirectional bus is used as the entire data bus in the 8-bit bidirectional mode or the least significant eight bits in the 16-bit mode. Under the 8-bit unidirectional mode, these bits are used as inputs for data, selected by the RxValid signal.
12
B3
XcvrSelect
Input
N/A
13
B4
TermSelect
Input
N/A
2
B1
Suspend
Input
N/A
Note 1. Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. Outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby.
Document #: 38-08052 Rev. *G
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CY7C68000A
Table 1. Pin Descriptions (continued) QFN VFBGA 24 B8 Name Tri_state Type Input Default Description[1] (continued) Tri-state Mode Enable Places the CY7C68000A into Tri-state mode which tri-states all outputs and IOs. Tri-state Mode can only be enabled while suspended. 0: Disables Tri-state Mode 1: Enables Tri-state Mode Line State These signals reflect the current state of the single-ended receivers. They are combinatorial until a "usable" CLK is available then they are synchronized to CLK. They directly reflect the current state of the DPLUS (LineState0) and DMINUS (LineState1). D- D+ Description 0 0 0: SE0 0 1 1: `J' State 1 0 2: `K' State 1 1 3: SE1 Line State These signals reflect the current state of the single-ended receivers. They are combinatorial until a `usable' CLK is available then they are synchronized to CLK. They directly reflect the current state of the DPLUS (LineState0) and DMINUS (LineState1). D- D+ Description 00-0: SE0 01-1: `J' State 10-2: `K' State 11-3: SE1 Operational Mode These signals select among various operational modes. 10 Description 00-0: Normal Operation 01-1: Non-driving 10-2: Disable Bit Stuffing and NRZI encoding 11-3: Reserved Operational Mode These signals select among various operational modes. 10 Description 00-0: Normal Operation 01-1: Non-driving 10-2: Disable Bit Stuffing and NRZI encoding 11-3: Reserved Transmit Valid This signal indicates that the data bus is valid. The assertion of Transmit Valid initiates SYNC on the USB. The negation of Transmit Valid initiates EOP on the USB. The start of SYNC must be initiated on the USB no less than one or no more that two CLKs after the assertion of TXValid. In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the USB between 8- and 16-bit times after the assertion of TXValid is detected by the Transmit State Machine. In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less than one or more than two CLKs after the assertion of TXValid is detected by the Transmit State Machine. Transmit Data Ready If TXValid is asserted, the SIE must always have data available for clocking in to the TX Holding Register on the rising edge of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of CLK, the CY7C68000A loads the data on the data bus into the TX Holding Register on the next rising edge of CLK. At that time, the SIE should immediately present the data for the next transfer on the data bus. Page 7 of 15
19
C2
LineState1
Output
18
C1
LineState0
Output
15
B6
OpMode1
Input
14
B5
OpMode0
Input
54
A5
TXValid
Input
1
A8
TXReady
Output
Document #: 38-08052 Rev. *G
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CY7C68000A
Table 1. Pin Descriptions (continued) QFN VFBGA 21 A4 Name RXValid Type Output Default Description[1] (continued) Receive Data Valid This signal indicates that the DataOut bus has valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the DataOut bus on the clock edge. Receive Active This signal indicates that the receive state machine has detected SYNC and is active. RXActive is negated after a bit stuff error or an EOP is detected. Receive Error 0 Indicates no error. 1 Indicates that a receive error has been detected. ValidH This signal indicates that the high-order eight bits of a 16-bit data word presented on the Data bus are valid. When DataBus16_8 = 1 and TXValid = 0, ValidH is an output, indicating that the high-order receive data byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid = 1, ValidH is an input and indicates that the high-order transmit data byte, presented on the Data bus by the transceiver, is valid. When DataBus16_8 = 0, ValidH is undefined. The status of the receive low-order data byte is determined by RXValid and are present on D0-D7. Data Bus 16_8 This signal selects between 8- and 16-bit data transfers. 1-16-bit data path operation enabled. CLK = 30 MHz. 0-8-bit data path operation enabled. When Uni_Bidi = 0, D[8:15] are undefined. When Uni_Bidi =1, D[0:7] are valid on TxValid and D[8:15] are valid on RxValid. CLK = 60 MHz Note: DataBus16_8 is static after Power-on Reset (POR) and is only sampled at the end of Reset. N/A Crystal Input Connect this signal to a 24 MHz parallel-resonant, fundamental mode crystal and 30 pF capacitor to GND. It is also correct to drive XTALIN with an external 24 MHz square wave derived from another clock source. Crystal Output Connect this signal to a 24 MHz parallel-resonant, fundamental mode crystal and 30 pF (nominal) capacitor to GND. If an external clock is used to drive XTALIN, leave this pin open. Driving this pin HIGH enables the unidirectional mode when the 8-bit interface is selected. Uni_Bidi is static after power-on reset (POR). VCC. Connect to 3.3V power source. N/A N/A N/A N/A N/A N/A N/A N/A N/A VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. VCC. Connect to 3.3V power source. Ground. Ground. Ground. Ground. Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground. Connect pin to Ground.
22
B7
RXActive
Output
23
A6
RXError
Output
56
A7
ValidH
I/O
51
A2
DataBus16_8
Input
6
H3
XTALIN
Input
5
H2
XTALOUT
Output
N/A
52 55 17 28 32 45 53 16 20 30 42 47 40 35 25
A3 C6 C7 D7 E7 E8 C4 C5 C3 D1 D2 G6 F7 F2 C8
Uni_Bidi VCC VCC VCC VCC VCC GND GND GND GND GND Reserved Reserved Reserved Reserved
Input Power Power Power Power Power Ground Ground Ground Ground Ground INPUT INPUT INPUT INPUT
Document #: 38-08052 Rev. *G
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CY7C68000A
Absolute Maximum Ratings
Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Supplied ..... 0C to +70C Supply Voltage to Ground Potential ...............-0.5V to +4.0V DC Input Voltage to Any Input Pin ............................. 5.25 V DC Voltage Applied to Outputs in High-Z State ..................................... -0.5V to VCC + 0.5V Power Dissipation .................................................... 630 mW Static Discharge Voltage .......................................... > 2000V Max Output Current, per IO pin ................................... 4 mA Max Output Current, all 21-IO pins ............................ 84 mA
Operating Conditions
TA (Ambient Temperature Under Bias) ............ 0C to +70C Supply Voltage ...............................................+3.0V to +3.6V Ground Voltage ................................................................. 0V FOSC (Oscillator or Crystal Frequency) ... 24 MHz 100 ppm ................................................................... Parallel Resonant
DC Characteristics
Table 2. DC Characteristics Parameter VCC VIH VIL II VOH VOL IOH IOL CIN CLOAD ISUSP ICC ICC tRESET Description Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Voltage High Output Low Voltage Output Current High Output Current Low Input Pin Capacitance Maximum Output Capacitance Suspend Current Supply Current HS Mode Supply Current FS Mode Minimum Reset time Except DPLUS/DMINUS/CLK DPLUS/DMINUS/CLK Output pins Connected[2] Disconnected[2] Normal operation OPMOD[1:0] = 00 Normal operation OPMOD[1:0] = 00 1.9 228 8 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA 2.4 0.4 4 4 10 15 30 273 35 175 90 Conditions Min 3.0 2 -0.5 Typ 3.3 Max 3.6 5.25 0.8 10 Unit V V V A V V mA mA pF pF pF A A mA mA ms
Note 2. Connected to the USB includes 1.5 Kohm internal pull up. Disconnected has the 1.5 Kohm internal pull up excluded.
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CY7C68000A
AC Electrical Characteristics
USB 2.0 Transceiver USB 2.0-compliant in FS and HS modes.
Timing Diagram HS/FS Interface Timing - 60 MHz
Figure 3. 60 MHz Interface Timing Constraints
CLK TCSU_MIN Control_In TDH_MIN TDSU_MIN DataIn TCCO Control_Out TCDO DataOut TCH_MIN
Table 3. 60 MHz Interface Timing Constraints Parameters Parameter TCSU_MIN TCH_MIN TDSU_MIN TDH_MIN TCCO TCDO Description Minimum setup time for TXValid Minimum hold time for TXValid Minimum setup time for Data (transmit direction) Minimum hold time for Data (transmit direction) Clock to Control out time for TXReady, RXValid, RXActive and RXError Clock to Data out time (Receive direction) Min 4 1 4 1 1 1 8 8 Typ Max Unit ns ns ns ns ns ns Notes
Document #: 38-08052 Rev. *G
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CY7C68000A
HS/FS Interface Timing - 30 MHz
Figure 4. 30 MHz Timing Interface Timing Constraints
CLK TCSU_MIN Control_In TDH_MIN TDSU_MIN DataIn TCDO TCCO TCVO TVH_MIN TVSU_MIN DataOut TCH_MIN
Control_Out
Table 4. 30 MHz Timing Interface Timing Constraints Parameters Parameter TCSU_MIN TCH_MIN TDSU_MIN TDH_MIN TCCO TCDO TVSU_MIN TVH_MIN TCVO Description Minimum setup time for TXValid Minimum hold time for TXValid Minimum setup time for Data (Transmit direction) Minimum hold time for Data (Transmit direction) Clock to Control Out time for TXReady, RXValid, RXActive and RXError Clock to Data out time (Receive direction) Minimum setup time for ValidH (transmit Direction) Minimum hold time for ValidH (Transmit direction) Clock to ValidH out time (Receive direction) Min 16 1 16 1 1 1 16 1 1 20 20 20 Typ Max Unit ns ns ns ns ns ns ns ns ns Notes
Figure 5. Tri-state Mode Timing Constraints
Ttssu Ttspd Suspend Tri-state Output / IO XXXX Hi-Z
Ttspd
Table 5. Tri-state Mode Timing Constraints Parameters Parameter Ttssu Ttspd Description Minimum setup time for Tri-state Propagation Delay for Tri-State mode Min 0 50 Typ Max Unit ns ns Notes
Document #: 38-08052 Rev. *G
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CY7C68000A
Ordering Information
Ordering Code CY7C68000A-56LFXC CY7C68000A-56BAXC CY3683 56 QFN 56 VFBGA MoBL-USB TX2 Development Board Package Type
Package Diagrams
The MoBL-USB TX2 is available in two packages:

56-pin QFN 56-pin VFBGA
Figure 6. 56-Pin Quad Flatpack No Lead Package 8 x 8 mm (Sawn Version) LS56B
51-85187 *C
Document #: 38-08052 Rev. *G
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CY7C68000A
Package Diagrams (continued)
Figure 7. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56
TOP VIEW
BOTTOM VIEW
O0.05 M C
PIN A1 CORNER
O0.15 M C A B O0.300.05(56X)
A1 CORNER
12 3 4 5 6 6 8 A B C D E F G H
87654321 A B C D E F G H 0.50 -B3.50
5.000.10
5.000.10
3.50
5.000.10
-A0.10(4X) 0.10 C
0.50
5.000.10
SIDE VIEW
0.45
0.080 C
REFERENCE JEDEC: MO-195C -C0.21 SEATING PLANE 0.160 ~0.260 1.0 max PACKAGE WEIGHT: 0.02 grams
001-03901-*B
PCB Layout Recommendations
Follow these recommendations to ensure reliable, high-performance operation[3].

Connections between the USB connector shell and signal ground must be done near the USB connector Bypass and flyback capacitors on VBus, near the connector, are recommended Keep DPLUS and DMINUS trace lengths within 2 mm of each other in length, with preferred length of 20 to 30 mm Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not split the plane under these traces Do not place vias on the DPLUS or DMINUS trace routing Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm
A four-layer impedance controlled board is required to maintain signal quality Specify impedance targets (ask your board vendor what they can achieve) To control impedance, maintain trace widths and trace spacing to within written specifications Minimize stubs to minimize reflected signals
Note 3. Source for recommendations: EZ-USB FX2TM PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Document #: 38-08052 Rev. *G
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CY7C68000A
Quad Flat Package No Leads (QFN) Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred from the MoBL-USB TX2 through the device's metal paddle on the package bottom. From here, heat is conducted to the PCB at the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by an array of via. A via is a plated through-hole in the PCB with a finished diameter of 13 mil. The QFN's metal die paddle must be soldered to the PCB's thermal pad. Solder mask is placed on the board top, over each via, to resist solder flow into the via. The mask on the top side also minimizes outgassing during the solder reflow process.
For further information on this package design, refer to the application note "Surface Mount Assembly of AMKOR's MicroLeadFrame (MLF) Technology." Download this application note from AMKOR's website, by following this link: http://www.amkor.com/products/notes_papers/MLFApp Note.pdf. The application note provides detailed information on board mounting guidelines, soldering flow, and rework process. Figure 8 displays a cross-sectional area under the package. The cross section is of only one via. The solder paste template needs to be designed to enable at least 50 percent solder coverage. The thickness of the solder paste template should be 5 mil. It is recommended that `No Clean', type 3 solder paste be used for mounting the part. Nitrogen purge is recommended during reflow. Figure 9 is a plot of the solder mask pattern image of the assembly (darker areas indicate solder).
Figure 8. Cross section of the Area Underneath the QFN Package
0.017" dia Solder Mask Cu Fill Cu Fill
PCB Material
0.013" dia
PCB Material
Via hole for thermally connecting the QFN to the circuit board ground plane.
This figure only shows the top three layers of the circuit board: Top Solder, PCB Dielectric, and the Ground Plane
Figure 9. Plot of the Solder Mask (White Area)
Document #: 38-08052 Rev. *G
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CY7C68000A
Document History Page
Document Title: CY7C68000A MoBL-USBTM TX2 USB 2.0 UTMI Transceiver Document Number: 38-08052 REV. ** *A *B *C *D *E *F *G ECN NO. 285592 427959 470121 476107 491668 498415 567869 2587010 Orig. of Change KKU TEH TEH TEH TEH TEH TEH KKU/PYRS Submission Date See ECN See ECN See ECN See ECN See ECN See ECN See ECN 10/13/08 New data sheet Addition of VFBGA Package information and Pinout, Removal of SSOP Package. Edited text and moved figure titles to the top per new template Change from preliminary to final data sheet. Grammatical and formatting changes This data sheet needs to be posted to the web site under NDA Addition of Tri-state Mode Update power consumption numbers Remove NDA requirement Update Pin 6 description on Page 8 Update template Description of Change
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(c) Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-08052 Rev. *G
Revised October 5, 2008
Page 15 of 15
MoBL-USB TX2 is a trademark of Cypress Semiconductor Corporation. Intel is a registered trademark of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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